1. Field of the Invention
The present invention relates to a method to form the ragged poly-silicon (poly-Si) structure for the DRAM cell, and more particularly, to a method for making a ragged poly-Si capacitor in the high density DRAM-cell.
2. Description of the Prior Art
Each semiconductor's memory cell consists typically of a storage capacitor and an access transistor. Since the basic element in the semiconductor's Dynamic Random Access Memory (DRAM) device is the memory cell, the manufacture of the memory-cell is essential to the DRAM. In fact, a memory-cell is provided for each bit stored by a DRAM-device. Either the source or the drain of the access transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor-gate-electrode are connected respectively to the external connecting-lines called a bit-line and a word-line. The other terminal of the capacitor is connected to a reference-voltage.
With the advent of Ultra Large Scale Integrated (ULSI) DRAM devices, the size of the memory cells has become smaller and smaller such that the area available for a single memory cell has become very small. The manufacture of a DRAM memory cell includes the fabrication of a transistor, a capacitor and contacts to periphery circuits. The devices of small area in the DRAM cell are thus most important for the designer. The planar capacitor is widely used in DRAM memory cells because the planar capacitor is relatively simple to fabricate yet the area of the planar capacitance is too big for the large-scale semiconductor device. Planar capacitors have been traditionally used due to their ease of manufacture, but as the memory cells decrease in size, the area of the planar capacitance also decreases. For very small size memory cells, it is not suitable to use the planar capacitance. Specifically, as the size of the capacitor decreases, the capacitance of the planar capacitor also decreases and the amount of the charge capable of being stored by the capacitor similarly decreases. This results in the capacitor being very susceptible to .alpha. particle interference.
Additionally, as the capacitance decreases, the charge held by the storage capacitor must be refreshed often. A simple stacked capacitor can not provide sufficient capacitance, even though high dielectric Ta.sub.2 O.sub.5 is used as the insulator between the plates of the capacitor. Also, when the trench capacitor is used, the "gated diode leakage" resulting in the loss of the charge stored in the capacitor will make the capacitor fail to hold the charge, and then the logic level is missed. By reducing the thickness of the dielectric layer, the capacitance of the capacitor can also be improved. Yet, the problems related with using very thin dielectric materials and the yield have limited the usage. The stacked capacitor and the trench capacitor are developed to overcome the aforementioned problems.
If a better structure that can increase the capacitance of the capacitor is utilized, even though there may be a loss of charge, the sufficient charges in the capacitor can still be kept in the proper logic level. Moreover, once a better capacitor structure is proposed, its capacitance can be further improved by either using a thinner dielectric insulator or by selecting an insulator having a higher dielectric constant. Thus, a cylindrical capacitor using the Hemispherical Grained Si has been proposed (see "A NEW CYLIDRICAL CAPACITOR USING HEMISPHERICAL GRAINED Si FOR 256 Mb DRAMs", H. Watanabe et al., Tech Dig, December 1992, pp.259-262).
The structure of the capacitor over bit line (COB) cell with a hemispherical grain (HSG--Si) poly-silicon storage node has been developed (see "CAPACITOR-OVER-BIT LINE CELL WITH HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs", M. Sakao et al., Microelectronics Research Laboratories, NEC Corporation. In IEDM Tech Dig., December 1990,pp. 655-658). This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufactured by optical delineation. The HSG--Si used to increase the effective area of the electrode of the capacitor is deposited by low-pressure chemical vapor deposition method at the transition temperature from amorphous Si to the polycrystalline Si. The HSG--Si storage node can be fabricated by addition of two process steps, i.e. HSG--Si deposition and an etchback. A HSG--Si electrode node has been proposed (see "A NEW CYLINDRICAL CAPACITOR USING HEMISPHERICAL GRAIN Si FOR 256 Mb DRAMs", H. Watanabe et al., Microelectronics Research Laboratories, NEC Corporation). After the electrode structure is formed, a native oxide on the electrode surface is removed by a diluted HF solution. HSG--Si appears on the silicon surface by using the seeding method.